Non-volatile memory (NVM) is a type of computer memory that retains stored information even after power cycling—powering a device off and then on again. In contrast, volatile memory is a type of computer memory that requires power to maintain the stored information—when the power is off or interrupted, the stored data is lost. A traditional type of non-volatile memory is a hard disk drive (HDD), which stores and accesses data using one or more rotating disks (platters) coated with magnetic material.
Another type of storage memory is a solid state drive (SSD), which differs from a HDD in that digital data is stored and retrieved using electronic circuits, without any moving mechanical parts. SSDs can be used based on both volatile memory, such as dynamic random-access memory (DRAM) or static random access memory (SRAM), or non-volatile memory, such as NAND flash memory. The standard NAND flash memory can be Single Level Cell (SLC) or Multi Level Cell (MLC), including enterprise MLC (eMLC), Triple Level Cell (TLC) and Quadratic Level Cell (QLC).
NAND flash memory devices typically apply error correction coding to data before it is stored. Error correction coding (ECC) is used to reduce bit errors in the data read from the memory device. Data is stored in and read from NAND flash memory devices in units of pages, and operating system file systems organize data in units of data clusters, such as 4 KB clusters. For example, a page in a NAND flash memory device might be nominally 16 KB but has some extra storage capacity or spare area, such as an extra 2 KB. In some cases, this spare area is sufficient to store the additional bits generated by error correction coding of the data being stored such that four 4 KB data clusters and the error correction bits for that user data can be stored in a single nominal 16 KB page. Higher-density NAND memory devices such as TLC and QLC typically have higher bit error rates, and thus require robust error correction coding. Robust error correction coding may also be used in NAND flash SSDs that are warrantied to satisfy a high performance criteria for a certain period of time, for example 100 GB of data writes per day (1 DWPD) for three years. In cases where strong error correction coding is applied, a 2 KB spare area of a nominal 16 KB flash page cannot always store the number of required error correction bits and so some of those error correction bits are stored in the user data area of the flash page. In such a situation four 4 KB clusters of user data and the error correction bits can no longer fit within a single page of NAND flash memory.
One possible technique addressing this problem would be to store the integer number of full data clusters) and all error correction bits for that data that can fit within one nominal 16 KB page of flash memory and leave any remaining portion of the page empty. But leaving portions of flash memory pages intentionally unused is inefficient and would result in the NAND flash SSD not meeting its capacity rating. Thus there is a need for a technique for efficiently managing the storage and retrieval of data with robust error correction coding in NAND flash memory devices.